1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device comprising forming n-type and p-type impurity regions in a semiconductor region.
2. Description of Related Art
A manufacturing process of CMOSFET includes a step of doping n-type impurities into a polycrystalline silicon film to be process into a gate electrode and a step of doping p-type impurities into the polycrystalline silicon film, wherein the n-type impurities are doped into an nMOS forming region of the polycrystalline silicon film and the p-type impurities are doped into a pMOS forming region of the polycrystalline silicon film (Jpn. Pat. Appln. KOKAI Publication No. H02-244629).
However, a joint portion of the nMOS forming region and the pMOS forming region, that is, a portion into which the n-type impurities and the p-type impurities are doped, has been needed to be taken into consideration along with the miniaturization of device. This problem appears more seriously in SRAM highly miniaturized.
The above problem will be explained concretely using FIGS. 16 to 19. FIGS. 16 to 19 are cross-sectional views of a gate process of conventional CMOSFET.
[FIG. 16]
An undoped polycrystalline silicon film 91 to be processed into a gate electrode is formed on an nMOS forming region and a pMOS forming region. The thickness of the polycrystalline silicon film 91 is 100 nm or greater. The polycrystalline silicon film 91 of the pMOS forming region is covered with a first photoresist mask 92. The thickness of the first photoresist mask 92 is 300 nm or greater (typically 600 nm or greater). N-type impurities (here, phosphorus ions) 93 are implanted into the polycrystalline silicon film 91 into the nMOS forming region by ion implantation process using the first photoresist mask 92 as a mask. As a result, an n-type impurities introduced region 94 is formed on a surface of the polycrystalline silicon film 91. The ion implantation process is carried out under conditions that acceleration energy is in a range of 5 to 10 keV, and a dose amount is 3-8×1015 cm−2.
[FIG. 17]
The first photoresist mask 92 is removed by using oxygen plasma ashing, and a liquid mixture of sulfuric acid and hydrogen peroxide solution. The polycrystalline silicon film 91 in the nMOS forming region is covered with a second photoresist mask 95. At that time, misalignment of mask is occurred in lithography step, and displacement between the second photoresist mask 95 and the n-type impurity introduced region 94 is occurred. Typically, the thickness of the second photoresist mask 95 is also 300 nm or greater. If the film thickness is thick, a taper is formed at the pattern edge of a photoresist film which has undergone baking process performed after the exposure process in the lithography step. In the ion implantation step after the lithography step, the taper causes the incident ion distribution to disperse under the photoresist mask 95. FIG. 17 shows a state where the second photoresist mask 95 is shifted rightward. As a result, a surface of left edge 96 of the n-type impurity introduced region 94 is exposed. The cause for the displacement of the second photoresist mask 95 is the misalignment of mask which occurred at the time of exposure performed to the underlying pattern of the semiconductor substrate through a glass mask.
[FIG. 18]
P-type impurities (here, boron ions) 97 are implanted into the polycrystalline silicon film 91 in the pMOS forming region by ion implantation process using the second photoresist mask 95 as a mask. As a result, a p-type impurities introduced region 98 is formed on a surface of the polycrystalline silicon film 91. The ion implantation process is carried out under the conditions that acceleration energy is 2 keV, and a dose amount is 5×1015 cm−2. At that time, since the second photoresist mask 95 is formed such that it is shifted rightward, an n-type and p-type impurities introduced region 99 of high impurity density (>1×1019 cm−3) including phosphorus and boron is formed between the n-type impurities introduced region 94 and the p-type impurities introduced region 98. Typically, the width of the n-type and p-type impurities introduced region 99 is 50 nm or greater.
[FIG. 19]
The second photoresist mask 95 is removed. Phosphorus and boron in the polycrystalline silicon film 91 are diffused by thermal treatment of 1000° C. or higher, and the phosphorus and boron are activated. As a result, three impurity regions, i.e., n-type impurity region 94′, p-type impurity region 98′, and the n-type and p-type impurity region 99′ are formed in the polycrystalline silicon film 91, then the undoped region in the polycrystalline silicon film 91 disappears.
Here, since the width of the n-type and p-type impurity region 99′ is 50 nm or more, it becomes difficult to control a threshold voltage of CMOSFET along with the miniaturization.
To reduce the width of the n-type and p-type impurity region 99′, mask alignment of higher precision is required. For this purpose, it is necessary to enhance the alignment precision of the exposure apparatus. However, much cost is required to develop an exposure apparatus having high alignment precision and thus, cost is increased at the manufacturing stage of devices.
To solve the above problem, there is a method in which a region where n-type impurities 93 are implanted and a region where p-type impurities 97 are implanted are deviated on a mask design so that the n-type impurity introduced region 94 and the p-type impurity introduced region 98 are not superposed on each other. However, this method has a problem that CAD correction work increases in a case of small lot production of many products such as SoC (System on Chip) because circuit pattern differs for each of products. Further, in some cases, it is very difficult to change the design, and a problem that the method cannot cope with the design occurs.